EPM3064ALC44-4N vs EPM3064ALC44-10N Vergleich
Detaillierter Direktvergleich von EPM3064ALC44-4N von Intel und EPM3064ALC44-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPM3064ALC44-4N - 64-Macrocell CPLD, 4.5ns, 44-PLCC | Intel
EPM3064ALC44-4N ⚠ Letzte BestellmöglichkeitAltera
EPM3064ALC44-10N - MAX 3000A CPLD, 64 Macrocells, 34 I/O | Intel / Altera
EPM3064ALC44-10N ObsoleteSpezifikationsvergleich
| Parameter | EPM3064ALC44-4N | EPM3064ALC44-10N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $4,80 | $4,25 |
| Family | MAX 3000A | — |
| Logic Elements / Macrocells | 64 macrocells | — |
| Logic Array Blocks (LABs) | 2 | 4 |
| Usable Gates | 1.25K | 1,250 |
| Number of I/O Pins | 34 | — |
| Propagation Delay (tPD) | 4.5 ns | 10 ns |
| Maximum Operating Frequency | 222.2 MHz | — |
| Supply Voltage - Core | 3.3 V | — |
| I/O Logic Level Support | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Program Memory Type | EEPROM (in-system programmable) | — |
| Programming Interface | IEEE Std 1149.1 JTAG | — |
| Gehäuse | 44-pin PLCC (J-lead) | 44-pin PLCC (LC44) |
| Montageart | Surface Mount | Surface Mount (PLCC socket compatible) |
| Betriebstemperatur | 0C to +70C (commercial) | [DATA_NEEDED: commercial / industrial grade] |
| Hot Socketing | Supported | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Product Family | — | MAX 3000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 64 |
| User I/O Pins | — | 34 |
| Maximum Counter Frequency | — | 227.3 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| I/O Bank Voltage (VCCIO) | — | 3.0 V to 3.6 V (MultiVolt) |
| Configuration Memory | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant) |
| Open-Drain Output Option | — | Yes (per I/O pin) |
| Output Slew-Rate Control | — | Programmable |