EPM3064ALC44-7N vs EPM3064ALC44-10N Vergleich
Detaillierter Direktvergleich von EPM3064ALC44-7N von Intel und EPM3064ALC44-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPM3064ALC44-7N - 64-Macrocell MAX 3000A CPLD, 7.5ns, 44-PLCC | Intel / Altera
EPM3064ALC44-7N ⚠ Letzte BestellmöglichkeitAltera
EPM3064ALC44-10N - MAX 3000A CPLD, 64 Macrocells, 34 I/O | Intel / Altera
EPM3064ALC44-10N ObsoleteSpezifikationsvergleich
| Parameter | EPM3064ALC44-7N | EPM3064ALC44-10N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $3,95 | $4,25 |
| Family | MAX 3000A | — |
| Logic IC Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 2 | 4 |
| Usable Gates | 1,250 | 1,250 |
| Number of User I/O Pins | 34 | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Maximum Frequency | 135.1 MHz | — |
| Core Technology | CMOS EEPROM | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.0 V to 3.6 V |
| I/O Tolerance | 5 V-tolerant | — |
| In-System Programmability | Yes (IEEE Std 1149.1 JTAG) | Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant) |
| Gehäuse | 44-pin PLCC | 44-pin PLCC (LC44) |
| Montageart | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| Betriebstemperatur | 0C to +70C (commercial) | [DATA_NEEDED: commercial / industrial grade] |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Compliant |
| Programming Software | Quartus II / Quartus Prime (legacy MAX+PLUS II supported) | — |
| Product Family | — | MAX 3000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| User I/O Pins | — | 34 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| I/O Bank Voltage (VCCIO) | — | 3.0 V to 3.6 V (MultiVolt) |
| Configuration Memory | — | CMOS EEPROM |
| Open-Drain Output Option | — | Yes (per I/O pin) |
| Output Slew-Rate Control | — | Programmable |