EPM3064ATC100-7N vs EPM3064AT100-10N Vergleich
Detaillierter Direktvergleich von EPM3064ATC100-7N von Altera und EPM3064AT100-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3064ATC100-7N | EPM3064AT100-10N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $6,10 | $5,45 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 2 | 4 |
| User I/O Pins | 66 | 66 |
| Usable Gates | up to 1,250 | 1,250 |
| Propagation Delay (tPD) | 7.5 ns (pin-to-pin, -7 speed grade) | — |
| Maximum Internal Frequency | 166.7 MHz (-7 speed grade) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| Program Memory Technology | EEPROM (non-volatile) | — |
| In-System Programming | IEEE Std. 1149.1 (JTAG), IEEE Std. 1532 | — |
| Gehäuse | TQFP-100 | TQFP-100 (T100), 14 mm x 14 mm |
| Montageart | Surface Mount | — |
| Betriebstemperatur | 0 °C to +70 °C (commercial) | — |
| RoHS-Status | [DATA_NEEDED: confirmed RoHS status from manufacturer page] | [DATA_NEEDED: RoHS compliance status] |
| Speed Grade | — | -10 (10 ns pin-to-pin delay) |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Bank Voltage | — | 3.3 V |
| 5 V Tolerant Inputs | — | Yes (via clamping diodes) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Programming Interface | — | JTAG (IEEE Std. 1149.1) with pin-locking |
| ISP Compliance | — | IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | IEEE Std. 1149.1 compliant |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Lead-Free | — | [DATA_NEEDED: lead-free finish] |