EPM3064ATC100-7N vs EPM3064ATC100-4N Vergleich
Detaillierter Direktvergleich von EPM3064ATC100-7N von Altera und EPM3064ATC100-4N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3064ATC100-7N | EPM3064ATC100-4N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $6,10 | $4,60 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | — |
| Logic Array Blocks (LABs) | 2 | — |
| User I/O Pins | 66 | 66 |
| Usable Gates | up to 1,250 | 1,250 |
| Propagation Delay (tPD) | 7.5 ns (pin-to-pin, -7 speed grade) | — |
| Maximum Internal Frequency | 166.7 MHz (-7 speed grade) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | 3.3 V or 2.5 V |
| Program Memory Technology | EEPROM (non-volatile) | — |
| In-System Programming | IEEE Std. 1149.1 (JTAG), IEEE Std. 1532 | — |
| Gehäuse | TQFP-100 | 100-pin TQFP |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0 °C to +70 °C (commercial) | 0C to +70C (commercial) |
| RoHS-Status | [DATA_NEEDED: confirmed RoHS status from manufacturer page] | [DATA_NEEDED: RoHS status] |
| Macro Cells | — | 64 |
| Logic Array Blocks | — | 2 |
| Pin-to-Pin Delay (tPD) | — | 4.5 ns |
| Counter Frequency | — | 222.2 MHz (max) |
| Supply Voltage (VCCINT) | — | 3.3 V |
| Programming Interface | — | IEEE Std. 1149.1 JTAG (ISP) |
| ISP Standard | — | IEEE Std. 1532 |
| Process Technology | — | CMOS EEPROM |