EPM3064ATC44-10 vs EPM3064ALC44-10N Vergleich
Detaillierter Direktvergleich von EPM3064ATC44-10 von Altera und EPM3064ALC44-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3064ALC44-10N - MAX 3000A CPLD, 64 Macrocells, 34 I/O | Intel / Altera
EPM3064ALC44-10N ObsoleteSpezifikationsvergleich
| Parameter | EPM3064ATC44-10 | EPM3064ALC44-10N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $4,35 | $4,25 |
| Family | MAX 3000A | — |
| Logic Elements / Macrocells | 64 macrocells | — |
| Usable Gates | 1,250 | 1,250 |
| Number of Logic Blocks / LABs | 4 LABs | — |
| Propagation Delay (tPD) | 10 ns | 10 ns |
| Maximum Internal Frequency | 227.3 MHz (counter speed) | — |
| Programmable I/Os | 34 | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) | 3.0 V to 3.6 V |
| I/O Bank Voltage (VCCIO) | MultiVolt 1.5 V / 1.8 V / 2.5 V / 3.3 V | 3.0 V to 3.6 V (MultiVolt) |
| Technology | CMOS EEPROM, 5 V tolerant I/O | — |
| In-System Programming | IEEE Std. 1532 (JTAG) | — |
| Boundary-Scan Support | IEEE 1149.1 (JTAG) | — |
| Gehäuse | TQFP-44, 10 x 10 mm, 0.8 mm pitch | 44-pin PLCC (LC44) |
| Montageart | Surface Mount | Surface Mount (PLCC socket compatible) |
| Betriebstemperaturbereich | 0C to +70C (commercial) | — |
| RoHS-Status | Non-compliant (legacy Altera, Pb-bearing) | Compliant |
| Product Family | — | MAX 3000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 64 |
| Logic Array Blocks (LABs) | — | 4 |
| User I/O Pins | — | 34 |
| Maximum Counter Frequency | — | 227.3 MHz |
| Configuration Memory | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant) |
| Betriebstemperatur | — | [DATA_NEEDED: commercial / industrial grade] |
| Open-Drain Output Option | — | Yes (per I/O pin) |
| Output Slew-Rate Control | — | Programmable |