EPM3064ATC44-10NAF vs EPM3032ATC44-10N Vergleich
Detaillierter Direktvergleich von EPM3064ATC44-10NAF von Altera und EPM3032ATC44-10N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3064ATC44-10NAF - 64-Macrocell MAX 3000A CPLD, 10ns TQFP-44 | Intel
EPM3064ATC44-10NAF NrndSpezifikationsvergleich
| Parameter | EPM3064ATC44-10NAF | EPM3032ATC44-10N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $5,05 | $2,46 |
| Series | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 64 | — |
| Logic Elements / LABs | 4 LABs (16 macrocells per LAB) | — |
| Usable Gates | 1250 | 600 |
| Number of I/O Pins | 34 | — |
| Propagation Delay (tPD, max) | 10 ns | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | — |
| I/O Voltage Tolerance | Multi-voltage (3.3 V / 2.5 V / 1.8 V capable) | — |
| Programmable Technology | EEPROM (non-volatile) | — |
| In-System Programmable | Yes (IEEE Std. 1532 compliant) | — |
| Boundary-Scan Test | Yes (IEEE Std. 1149.1 JTAG) | — |
| Pin-Locking | Yes | — |
| Gehäuse | TQFP-44 (10x10 mm) | 44-pin TQFP |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | [DATA_NEEDED: industrial/commercial grade] | — |
| Lead Finish | Lead-free (NiPdAu, AF suffix) | — |
| RoHS-Status | Compliant | Compliant (lead-free) |
| Configuration Memory Cycles | 100 erase/program cycles | — |
| Device Family | — | CPLD - Complex Programmable Logic Device |
| Macrocells | — | 32 |
| Logic Array Blocks (LABs) | — | 2 |
| User I/O Pins | — | 34 |
| Pin-to-Pin Logic Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency (fCNT) | — | 138.9 MHz |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Logic Level Support | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| In-System Programmability | — | Yes, IEEE 1149.1 JTAG |
| ISP Standard Compliance | — | IEEE Std. 1532 |
| Open-Drain I/O Option | — | Yes, per pin |
| Configuration Memory | — | EEPROM (non-volatile, instant-on) |
| Operating Temperature (Commercial) | — | 0 C to +70 C |