EPM3064ATC44-7 vs EPM3064ATC44-7N Vergleich
Detaillierter Direktvergleich von EPM3064ATC44-7 von Altera und EPM3064ATC44-7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3064ATC44-7 | EPM3064ATC44-7N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $4,20 | $2,30 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | — |
| Logic Array Blocks | 4 | 2 |
| Usable Gates | 1.25K | 1,250 |
| User I/O Pins | 34 | 34 |
| Pin-Anzahl | 44 | — |
| Gehäuse | TQFP-44 | 44-pin TQFP |
| Speed Grade | -7 (7.5 ns tPD) | -7 (7.5 ns pin-to-pin delay) |
| Pin-to-Pin Propagation Delay | 7.5 ns | — |
| Maximum Counter Frequency | 192.3 MHz | 192.3 MHz (-7 grade) |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Logic Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | — |
| Process Technology | CMOS EEPROM | — |
| Betriebstemperatur | 0C to +70C (Commercial) | 0°C to +85°C (commercial) |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | unknown | Compliant |
| Macro Cells | — | 64 |
| Anzahl der Pins | — | 44 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Supply Voltage (VCC) | — | 3.3 V |
| MultiVolt I/O | — | 1.8 V / 2.5 V / 3.3 V |
| Programmability | — | EEPROM, in-system programmable (ISP) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| ISP Standard | — | IEEE Std. 1532 compliant |
| Boundary-Scan Test (BST) | — | Built-in, JTAG-driven |