EPM3064ATI44-10 vs EPM3064ATC44-10N Vergleich
Detaillierter Direktvergleich von EPM3064ATI44-10 von Intel und EPM3064ATC44-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3064ATI44-10 | EPM3064ATC44-10N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,65 | $5,10 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Programmable Type | In-System Programmable (ISP), EEPROM-based | — |
| Number of Macrocells | 64 | — |
| Number of Logic Array Blocks (LABs) | 4 | — |
| Number of Usable Gates | 1,250 | — |
| Number of User I/O Pins | 34 | — |
| Gehäuse | TQFP-44 (10x10 mm, 0.8 mm pitch) | TQFP-44 (10x10 mm) |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns |
| Maximum Counter Frequency | 227.3 MHz | 192.3 MHz |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Voltage Tolerance | 5.0 V tolerant (MultiVolt I/O) | — |
| JTAG Interface | IEEE Std. 1149.1 compliant | — |
| ISP Standard | IEEE Std. 1532 | — |
| Betriebstemperatur | -40C to +85C (Industrial) | 0C to +70C (commercial) |
| RoHS-Status | Non-Compliant (contains lead, per DigiChip listing) | Compliant |
| Lead Free Status | Contains Lead | — |
| Montageart | Surface Mount | Surface Mount |
| Process Technology | CMOS, EEPROM | — |
| Programming Cycles | [DATA_NEEDED: typical program/erase endurance] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 1250 |
| Macro Cells | — | 64 |
| User I/O Pins | — | 34 |
| Logic Array Blocks (LABs) | — | 4 |
| I/O Standard | — | MultiVolt (mixed 1.5 V / 1.8 V / 2.5 V / 3.3 V) |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programming | — | IEEE Std. 1532 compliant |
| Boundary-Scan Test | — | IEEE Std. 1149.1 (JTAG) compliant |
| Pin-Locking | — | Yes (across design iterations) |