EPM3128ATC144-7 vs EPM3128ATC144-5N Vergleich
Detaillierter Direktvergleich von EPM3128ATC144-7 von Intel und EPM3128ATC144-5N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3128ATC144-5N - MAX 3000A 128-Macro 5ns CPLD | Altera
EPM3128ATC144-5N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM3128ATC144-7 | EPM3128ATC144-5N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,10 | $13,75 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | 2500 |
| Logic Array Blocks (LABs) | 8 (16 macrocells each) | — |
| User I/Os | 96 | — |
| Gehäuse | TQFP-144 (22x22 mm) | 144-pin TQFP (20x20 mm) |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V (multiVolt) | — |
| Speed Grade | -7 | — |
| Pin-to-Pin Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Internal Frequency (fCNT) | 129.9 MHz | — |
| Programming Technology | CMOS EEPROM (in-system programmable) | — |
| JTAG Support | IEEE 1149.1 boundary-scan + ISP | — |
| Betriebstemperatur | 0C to +70C (Commercial) | 0C to 70C (Commercial) |
| Montageart | Surface Mount | Surface Mount |
| Process Technology | CMOS EEPROM | — |
| Logic Family | — | CMOS |
| User I/O | — | 96 |
| Pin-to-Pin Logic Delay | — | 5 ns |
| Counter Frequency | — | up to 227.3 MHz |
| Supply Voltage (Core) | — | 3.3 V |
| I/O Logic Levels Supported | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| In-System Programmability | — | Yes (3.3-V via JTAG) |
| JTAG Boundary Scan | — | IEEE Std 1149.1 compliant |
| RoHS-Status | — | Compliant (lead-free) |