EPM3256AFC256-10 vs EPM3512AFC256C Vergleich
Detaillierter Direktvergleich von EPM3256AFC256-10 von Altera und EPM3512AFC256C von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3256AFC256-10 - 256-Macro CPLD MAX 3000A | Intel / Altera | FBGA-256
EPM3256AFC256-10 ⚠ Letzte BestellmöglichkeitIntel
EPM3512AFC256C - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera
EPM3512AFC256C ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM3256AFC256-10 | EPM3512AFC256C |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $19,95 | $27,95 |
| Family | MAX 3000A | MAX 3000A |
| Logic Family | CMOS (EEPROM-based) | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 256 | — |
| Usable Gates | 5,000 | — |
| Logic Array Blocks (LABs) | 16 (16 macrocells each) | 16 |
| Maximum User I/Os | 161 | 208 |
| Propagation Delay (tPD) | 10 ns | — |
| Internal Counter Frequency (fCNT) | 95.2 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage Tolerance | 5.0 V tolerant | — |
| In-System Programmability | Yes (3.3 V ISP via JTAG IEEE 1149.1) | — |
| Betriebstemperatur | 0°C to +70°C (Commercial) | 0C to +70C (Commercial) |
| Gehäuse | 256-ball FBGA (Fine-Line BGA) | 256-ball FineLine BGA (FC) |
| Pitch | [DATA_NEEDED: BGA ball pitch] | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Macrocells | — | 512 |
| Dedicated Input Pins | — | 12 |
| Speed Grade | — | C (per datasheet ordering code) |
| Configuration Technology | — | EEPROM (non-volatile, instant-on) |
| Core Voltage | — | 3.3 V |
| I/O Standards Supported | — | MultiVolt: 5.0 V, 3.3 V, 2.5 V |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |
| PCI Compliance | — | PCI SIG Local Bus Specification Revision 2.2 |
| Programming | — | In-system programmable via JTAG |