EPM3256ATC144-10 vs EPM3256ATC144-7 Vergleich
Detaillierter Direktvergleich von EPM3256ATC144-10 von Intel und EPM3256ATC144-7 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPM3256ATC144-10 - 256-Macrocell CPLD, 10ns, 144-TQFP | Intel / Altera
EPM3256ATC144-10 ObsoleteSpezifikationsvergleich
| Parameter | EPM3256ATC144-10 | EPM3256ATC144-7 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $17,06 |
| Manufacturer | Intel (formerly Altera) | — |
| Series | MAX 3000A | — |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Programmable Type | In-System Programmable (EEPROM-based, IEEE 1532) | — |
| Macrocells | 256 | 256 |
| Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | 5,000 | — |
| Number of I/O Pins | 116 | — |
| Propagation Delay (tpd max) | 10 ns | — |
| Counter Frequency (max) | 95.2 MHz | — |
| Core Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) | — |
| I/O Logic Level Support | MultiVolt - 5.0 V, 3.3 V, 2.5 V | — |
| Betriebstemperatur | 0 C to +70 C (Commercial) | 0C to +70C (Commercial) |
| Gehäuse | 144-pin TQFP (20x20 mm) | TQFP-144 (LFQFP, gull-wing) |
| Montageart | Surface Mount | Surface Mount |
| JTAG / Boundary Scan | Yes (IEEE 1149.1) | — |
| Process Technology | CMOS EEPROM | — |
| RoHS-Status | Non-compliant (original EPM3256ATC144-10); N suffix variant is lead-free | — |
| Family | — | MAX 3000A |
| User I/Os | — | 116 |
| Logic Elements / Gates | — | 600 to 10,000 usable gates |
| Propagation Delay (tPD) | — | 7.5 ns |
| Counter Frequency (fCNT) | — | 227.3 MHz |
| Speed Grade | — | -7 |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| Supply Voltage - I/O (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V |
| In-System Programming | — | IEEE Std. 1532 compliant, 3.3 V ISP |
| Pin-Anzahl | — | 144 |
| PCI Compliance | — | PCI Local Bus Specification Revision 2.2 (speed grades -4 to -10) |
| JTAG Support | — | IEEE Std. 1149.1 boundary-scan |