EPM3256ATC144-10N vs EPM3256ATI144-7N Vergleich
Detaillierter Direktvergleich von EPM3256ATC144-10N von Altera und EPM3256ATI144-7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera
EPM3256ATC144-10N ⚠ Letzte BestellmöglichkeitAltera
EPM3256ATI144-7N - 256-Macrocell MAX 3000A CPLD, 7.5ns, TQFP-144 | Altera
EPM3256ATI144-7N ObsoleteSpezifikationsvergleich
| Parameter | EPM3256ATC144-10N | EPM3256ATI144-7N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $14,50 | $10,95 |
| Series | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 256 | — |
| Usable Gates | 5,000 (up to 10,000 usable in family) | 5,000 |
| Number of I/Os | 116 | — |
| Number of Logic Elements / Blocks | 16 LABs | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Propagation Delay (tPD) | 10 ns | 7.5 ns (typical) |
| Maximum Counter Frequency | 227.3 MHz | — |
| Global Clocks | 3 | — |
| Global Clear / OE | Yes (1 global clear, 1 global OE) | — |
| Program Memory Type | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Support | IEEE Std. 1149.1 with pin-locking | — |
| ISP Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | — |
| Gehäuse | 144-LQFP (TQFP, ATC suffix) | TQFP-144 (20 x 20 mm, 0.5 mm pitch) |
| Montageart | Surface Mount | — |
| Betriebstemperatur | 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix] | -40C to +85C (industrial) |
| RoHS-Status | [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data] | Compliant (lead-free) |
| Lead-Free / Halogen-Free | [DATA_NEEDED: not explicitly confirmed in verified data] | — |
| Family | — | MAX 3000A |
| Macrocells | — | 256 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 116 |
| Maximum Internal Frequency | — | 126.6 MHz |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 2.5 V |
| MultiVolt I/O Logic Levels | — | 5.0 V / 3.3 V / 2.5 V |
| Programming Technology | — | EEPROM (in-system programmable) |
| JTAG / ISP | — | IEEE Std. 1532 compliant |
| Boundary Scan | — | IEEE Std. 1149.1 (JTAG) |
| Hot-Socketing Support | — | Yes |