EPM3256ATC144-10N vs EPM3512ATC144-10N Vergleich
Detaillierter Direktvergleich von EPM3256ATC144-10N von Altera und EPM3512ATC144-10N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera
EPM3256ATC144-10N ⚠ Letzte BestellmöglichkeitIntel
EPM3512ATC144-10N - MAX 3000A CPLD, 512 Macrocells, 144-TQFP | Intel
EPM3512ATC144-10N ✓ AktivSpezifikationsvergleich
| Parameter | EPM3256ATC144-10N | EPM3512ATC144-10N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $14,50 | $18,75 |
| Series | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 256 | — |
| Usable Gates | 5,000 (up to 10,000 usable in family) | 10000 |
| Number of I/Os | 116 | — |
| Number of Logic Elements / Blocks | 16 LABs | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Propagation Delay (tPD) | 10 ns | 10 ns |
| Maximum Counter Frequency | 227.3 MHz | — |
| Global Clocks | 3 | — |
| Global Clear / OE | Yes (1 global clear, 1 global OE) | — |
| Program Memory Type | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Support | IEEE Std. 1149.1 with pin-locking | — |
| ISP Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | — |
| Gehäuse | 144-LQFP (TQFP, ATC suffix) | 144-pin TQFP (TC144) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix] | 0C to +70C (commercial, N suffix) |
| RoHS-Status | [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data] | [DATA_NEEDED: RoHS compliance from datasheet] |
| Lead-Free / Halogen-Free | [DATA_NEEDED: not explicitly confirmed in verified data] | — |
| Family | — | MAX 3000A |
| Macrocells | — | 512 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O | — | 212 |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fMAX in MHz] |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5 V (MultiVolt) |
| Configuration Memory | — | Non-volatile EEPROM |
| Programming Interface | — | JTAG (IEEE 1149.1), in-system programmable |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |