EPM3256ATC144-7N vs EPM3256ATC144-10N Vergleich
Detaillierter Direktvergleich von EPM3256ATC144-7N von Altera und EPM3256ATC144-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3256ATC144-7N - MAX 3000A CPLD 256 Macro 7.5ns | Altera
EPM3256ATC144-7N ⚠ Letzte BestellmöglichkeitAltera
EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera
EPM3256ATC144-10N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM3256ATC144-7N | EPM3256ATC144-10N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,20 | $14,50 |
| Family | MAX 3000A | — |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 256 | 256 |
| Logic Gates (usable) | 5,000 | — |
| Number of Logic Array Blocks (LABs) | 16 | — |
| User I/Os | 116 | — |
| Propagation Delay (tPD) | 7.5 ns | 10 ns |
| Maximum Internal Frequency | 126.6 MHz | — |
| Supply Voltage (VCCIO) | 3.0 V to 3.6 V | — |
| Programmable Logic Technology | CMOS EEPROM-based | — |
| In-System Programmable (ISP) | Yes (3.3 V) | — |
| Betriebstemperatur | 0C to +70C (Commercial) | 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix] |
| Gehäuse | 144-pin TQFP | 144-LQFP (TQFP, ATC suffix) |
| Montageart | Surface Mount | Surface Mount |
| Logic Family | CMOS | — |
| JTAG Support | IEEE 1149.1 boundary-scan | IEEE Std. 1149.1 with pin-locking |
| RoHS-Status | Compliant | [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data] |
| Series | — | MAX 3000A |
| Usable Gates | — | 5,000 (up to 10,000 usable in family) |
| Number of I/Os | — | 116 |
| Number of Logic Elements / Blocks | — | 16 LABs |
| Supply Voltage (VCCINT) | — | 3.3 V |
| Maximum Counter Frequency | — | 227.3 MHz |
| Global Clocks | — | 3 |
| Global Clear / OE | — | Yes (1 global clear, 1 global OE) |
| Program Memory Type | — | EEPROM (non-volatile, in-system programmable) |
| ISP Compliance | — | IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Built-in, IEEE 1149.1 compliant |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: not explicitly confirmed in verified data] |