EPM3256ATC144-7N vs EPM3256ATI144-7N Vergleich
Detaillierter Direktvergleich von EPM3256ATC144-7N von Altera und EPM3256ATI144-7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3256ATC144-7N - MAX 3000A CPLD 256 Macro 7.5ns | Altera
EPM3256ATC144-7N ⚠ Letzte BestellmöglichkeitAltera
EPM3256ATI144-7N - 256-Macrocell MAX 3000A CPLD, 7.5ns, TQFP-144 | Altera
EPM3256ATI144-7N ObsoleteSpezifikationsvergleich
| Parameter | EPM3256ATC144-7N | EPM3256ATI144-7N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,20 | $10,95 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 256 | — |
| Logic Gates (usable) | 5,000 | — |
| Number of Logic Array Blocks (LABs) | 16 | — |
| User I/Os | 116 | — |
| Propagation Delay (tPD) | 7.5 ns | 7.5 ns (typical) |
| Maximum Internal Frequency | 126.6 MHz | 126.6 MHz |
| Supply Voltage (VCCIO) | 3.0 V to 3.6 V | — |
| Programmable Logic Technology | CMOS EEPROM-based | — |
| In-System Programmable (ISP) | Yes (3.3 V) | — |
| Betriebstemperatur | 0C to +70C (Commercial) | -40C to +85C (industrial) |
| Gehäuse | 144-pin TQFP | TQFP-144 (20 x 20 mm, 0.5 mm pitch) |
| Montageart | Surface Mount | — |
| Logic Family | CMOS | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| RoHS-Status | Compliant | Compliant (lead-free) |
| Macrocells | — | 256 |
| Usable Gates | — | 5,000 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 116 |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 2.5 V |
| MultiVolt I/O Logic Levels | — | 5.0 V / 3.3 V / 2.5 V |
| Programming Technology | — | EEPROM (in-system programmable) |
| JTAG / ISP | — | IEEE Std. 1532 compliant |
| Boundary Scan | — | IEEE Std. 1149.1 (JTAG) |
| Hot-Socketing Support | — | Yes |