EPM3256ATI144-10 vs EPM3256ATC144-7 Vergleich
Detaillierter Direktvergleich von EPM3256ATI144-10 von Intel und EPM3256ATC144-7 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3256ATI144-10 | EPM3256ATC144-7 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $17,06 |
| Series | MAX 3000A | — |
| Programmable Type | In-System Programmable (ISP), EEPROM-based | — |
| Number of Macrocells | 256 | — |
| Number of Logic Elements / Blocks | 16 LABs (Logic Array Blocks) | — |
| Number of Gates | 5,000 typical usable gates | — |
| Number of User I/O | 116 | — |
| Propagation Delay (tpd max) | 10 ns | — |
| Maximum Frequency (fmax) | 95.2 MHz | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) | — |
| I/O Voltage Support | MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V mixed | — |
| Logic Family | CMOS, EEPROM-based | — |
| Betriebstemperatur | -40°C to +85°C (industrial) | 0C to +70C (Commercial) |
| Gehäuse | 144-pin TQFP (20x20 mm) | TQFP-144 (LFQFP, gull-wing) |
| Montageart | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) and IEEE Std. 1532 ISP | — |
| Compliance | IEEE Std. 1532 ISP, PCI-compatible I/O | — |
| Lebenszyklusstatus | Obsolete (per HighqualityPCB listing) | — |
| Family | — | MAX 3000A |
| Macrocells | — | 256 |
| User I/Os | — | 116 |
| Logic Elements / Gates | — | 600 to 10,000 usable gates |
| Propagation Delay (tPD) | — | 7.5 ns |
| Counter Frequency (fCNT) | — | 227.3 MHz |
| Speed Grade | — | -7 |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| Supply Voltage - I/O (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V |
| In-System Programming | — | IEEE Std. 1532 compliant, 3.3 V ISP |
| Pin-Anzahl | — | 144 |
| PCI Compliance | — | PCI Local Bus Specification Revision 2.2 (speed grades -4 to -10) |
| JTAG Support | — | IEEE Std. 1149.1 boundary-scan |