EPM3256ATI144-10N vs EPM3256ATC144-7N Vergleich
Detaillierter Direktvergleich von EPM3256ATI144-10N von Altera und EPM3256ATC144-7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3256ATC144-7N - MAX 3000A CPLD 256 Macro 7.5ns | Altera
EPM3256ATC144-7N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM3256ATI144-10N | EPM3256ATC144-7N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,25 | $17,20 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD - Complex Programmable Logic Device |
| Macrocells | 256 | — |
| Usable Gates | 5,000 | — |
| User I/Os | 116 | 116 |
| Logic Blocks / Logic Elements | 16 | — |
| Propagation Delay (tPD) | 10 ns | 7.5 ns |
| Max Frequency (fMAX) | 95.2 MHz | — |
| Supply Voltage - Core | 3.3 V | — |
| I/O Voltage Support | 1.8 V / 2.5 V / 3.3 V (multi-voltage) | — |
| In-System Programmability | Yes, IEEE Std. 1532 compliant | — |
| Boundary-Scan Test (BST) | Yes, IEEE Std. 1149.1 (JTAG) | — |
| Gehäuse | 144-pin TQFP | 144-pin TQFP |
| Betriebstemperatur | -40 C to +85 C (industrial, "I" suffix) | 0C to +70C (Commercial) |
| Lead-Free / Pb-Free | Yes ("N" suffix) | — |
| RoHS-Status | Compliant | Compliant |
| Process Technology | CMOS EEPROM-based, non-volatile | — |
| Montageart | Surface Mount | Surface Mount |
| MSL-Level | 3 (per JEDEC J-STD-020, typical for TQFP) | — |
| Macro Cells | — | 256 |
| Logic Gates (usable) | — | 5,000 |
| Number of Logic Array Blocks (LABs) | — | 16 |
| Maximum Internal Frequency | — | 126.6 MHz |
| Supply Voltage (VCCIO) | — | 3.0 V to 3.6 V |
| Programmable Logic Technology | — | CMOS EEPROM-based |
| In-System Programmable (ISP) | — | Yes (3.3 V) |
| Logic Family | — | CMOS |
| JTAG Support | — | IEEE 1149.1 boundary-scan |