EPM3512AFC-7N vs EPM3512AFC256-10 Vergleich
Detaillierter Direktvergleich von EPM3512AFC-7N von Intel und EPM3512AFC256-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPM3512AFC-7N - 512-Macrocell MAX 3000A CPLD, 7.5ns, BGA-256 | Intel (Altera)
EPM3512AFC-7N ✓ Aktiv
Spezifikationsvergleich
| Parameter | EPM3512AFC-7N | EPM3512AFC256-10 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $26,40 | $17,50 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| User I/Os | 208 | — |
| Dedicated Inputs | 16 | — |
| Propagation Delay (tPD) | 7.5 ns (speed grade -7) | — |
| Gehäuse | BGA-256 (FineLine BGA) | 256-pin FBGA |
| Logic Family | CMOS, EEPROM-based | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant | — |
| In-System Programmability | Yes - IEEE Std. 1532 / JTAG (IEEE 1149.1) | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) |
| Programming Interface | JTAG (4-wire TCK/TMS/TDI/TDO) | — |
| Betriebstemperatur | 0 C to +70 C (commercial) | — |
| Montageart | Surface Mount (BGA) | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS status] | unknown |
| Usable Gates | — | 10,000 |
| Maximum I/O Pins | — | 208 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 87 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5-V tolerant |
| Programmable Technology | — | CMOS EEPROM |
| Betriebstemperaturbereich | — | [DATA_NEEDED: industrial/commercial operating temperature range] |
| Pin-Anzahl | — | 256 |
| Architecture | — | MAX (Multiple Array matriX) EEPROM-based |