EPM3512AFC256-10 vs EPM3512AFC-7N Vergleich
Detaillierter Direktvergleich von EPM3512AFC256-10 von Altera und EPM3512AFC-7N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPM3512AFC-7N - 512-Macrocell MAX 3000A CPLD, 7.5ns, BGA-256 | Intel (Altera)
EPM3512AFC-7N ✓ AktivSpezifikationsvergleich
| Parameter | EPM3512AFC256-10 | EPM3512AFC-7N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,50 | $26,40 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Usable Gates | 10,000 | — |
| Maximum I/O Pins | 208 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 87 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage Tolerance | 5-V tolerant | — |
| Programmable Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) | Yes - IEEE Std. 1532 / JTAG (IEEE 1149.1) |
| Gehäuse | 256-pin FBGA | BGA-256 (FineLine BGA) |
| Betriebstemperaturbereich | [DATA_NEEDED: industrial/commercial operating temperature range] | — |
| Pin-Anzahl | 256 | — |
| Montageart | Surface Mount | Surface Mount (BGA) |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS status] |
| Architecture | MAX (Multiple Array matriX) EEPROM-based | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| User I/Os | — | 208 |
| Dedicated Inputs | — | 16 |
| Propagation Delay (tPD) | — | 7.5 ns (speed grade -7) |
| Logic Family | — | CMOS, EEPROM-based |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant |
| Programming Interface | — | JTAG (4-wire TCK/TMS/TDI/TDO) |
| Betriebstemperatur | — | 0 C to +70 C (commercial) |