EPM3512AFC256-10 vs EPM3512AFC256-19 Vergleich
Detaillierter Direktvergleich von EPM3512AFC256-10 von Altera und EPM3512AFC256-19 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3512AFC256-10 | EPM3512AFC256-19 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,50 | $10,85 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Usable Gates | 10,000 | 10000 |
| Maximum I/O Pins | 208 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | 7.5 ns |
| Maximum Counter Frequency | 87 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage Tolerance | 5-V tolerant | — |
| Programmable Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) | — |
| Gehäuse | 256-pin FBGA | 256-ball FineLine BGA (FC) |
| Betriebstemperaturbereich | [DATA_NEEDED: industrial/commercial operating temperature range] | — |
| Pin-Anzahl | 256 | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS status] |
| Architecture | MAX (Multiple Array matriX) EEPROM-based | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum Operating Frequency | — | 80 MHz |
| Speed Grade | — | -19 |
| User I/O Pins | — | 208 |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Supply Voltage VCCIO | — | 2.5 V or 3.3 V (5.0 V tolerant inputs) |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP (IEEE 1532) |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| Betriebstemperatur | — | -40C to +85C (industrial) |
| Non-volatile Configuration | — | Yes (EEPROM-based) |