EPM3512AFC256-10 vs EPM3512AFC256-22 Vergleich
Detaillierter Direktvergleich von EPM3512AFC256-10 von Altera und EPM3512AFC256-22 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3512AFC256-10 | EPM3512AFC256-22 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,50 | $16,10 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Usable Gates | 10,000 | — |
| Maximum I/O Pins | 208 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 87 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage Tolerance | 5-V tolerant | — |
| Programmable Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) | — |
| Gehäuse | 256-pin FBGA | FC-256 (FineLine BGA, 256 balls, 1.0 mm pitch) |
| Betriebstemperaturbereich | [DATA_NEEDED: industrial/commercial operating temperature range] | — |
| Pin-Anzahl | 256 | — |
| Montageart | Surface Mount | Surface Mount (BGA) |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS compliance status] |
| Architecture | MAX (Multiple Array matriX) EEPROM-based | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum User I/O Pins | — | 208 (typical for FC256 package) |
| Speed Grade | — | -22 (tPD ~22 ns) |
| Propagation Delay (tPD) | — | 22 ns |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Standards Supported | — | 2.5 V, 3.3 V, 5.0 V (VCCIO selectable) |
| In-System Programming | — | IEEE Std. 1532-compliant ISP via JTAG |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |
| Betriebstemperatur | — | [DATA_NEEDED: operating temperature grade] |