EPM3512AFC256-18 vs EPM3256AFC256-10 Vergleich
Detaillierter Direktvergleich von EPM3512AFC256-18 von Altera und EPM3256AFC256-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3512AFC256-18 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-18 ObsoleteAltera
EPM3256AFC256-10 - 256-Macro CPLD MAX 3000A | Intel / Altera | FBGA-256
EPM3256AFC256-10 ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM3512AFC256-18 | EPM3256AFC256-10 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,20 | $19,95 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | — |
| Logic Array Blocks (LABs) | 16 | 16 (16 macrocells each) |
| Maximum User I/O Pins | 212 | — |
| Pin-to-Pin Delay (tPD1) | 18 ns | — |
| Global Clock Networks | 4 | — |
| VCCINT (Core Supply) | 3.0 V to 3.6 V (3.3 V typical) | — |
| VCCIO (I/O Supply) | 2.5 V or 3.3 V (MultiVolt) | — |
| Betriebstemperatur | [DATA_NEEDED: industrial/commercial grade] | 0°C to +70°C (Commercial) |
| Programming Technology | EEPROM (non-volatile) | — |
| In-System Programming | IEEE Std. 1532 / JTAG (IEEE Std. 1149.1) | — |
| Gehäuse | 256-ball FineLine BGA (FCBGA) | 256-ball FBGA (Fine-Line BGA) |
| Ball Pitch | 1.0 mm | — |
| RoHS-Status | [DATA_NEEDED: not specified in retrieved data] | [DATA_NEEDED: RoHS compliance status] |
| Montageart | Surface Mount | Surface Mount |
| Logic Family | — | CMOS (EEPROM-based) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 256 |
| Usable Gates | — | 5,000 |
| Maximum User I/Os | — | 161 |
| Propagation Delay (tPD) | — | 10 ns |
| Internal Counter Frequency (fCNT) | — | 95.2 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5.0 V tolerant |
| In-System Programmability | — | Yes (3.3 V ISP via JTAG IEEE 1149.1) |
| Pitch | — | [DATA_NEEDED: BGA ball pitch] |