EPM3512AFC256-21 vs EPM3512AFC256-18 Vergleich
Detaillierter Direktvergleich von EPM3512AFC256-21 von Altera und EPM3512AFC256-18 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3512AFC256-18 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-18 ObsoleteSpezifikationsvergleich
| Parameter | EPM3512AFC256-21 | EPM3512AFC256-18 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $18,75 | $17,20 |
| Device Family | MAX 3000A | — |
| Logic Elements / Macrocells | 512 macrocells | — |
| Usable Gates | 10,000 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum Operating Frequency | 87 MHz | — |
| Gehäuse | FBGA-256 (FineLine BGA) | 256-ball FineLine BGA (FCBGA) |
| Betriebstemperatur | -40C to +85C (industrial) | [DATA_NEEDED: industrial/commercial grade] |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) | — |
| Programmable Pins (max) | [DATA_NEEDED: maximum user I/O pin count] | — |
| Programming Interface | JTAG / IEEE Std. 1532 ISP | — |
| Speichertyp | Non-volatile EPROM/EEPROM cell array | — |
| Montageart | Surface Mount (BGA) | Surface Mount |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not specified in retrieved data] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 3000A |
| Macrocells | — | 512 |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Delay (tPD1) | — | 18 ns |
| Global Clock Networks | — | 4 |
| VCCINT (Core Supply) | — | 3.0 V to 3.6 V (3.3 V typical) |
| VCCIO (I/O Supply) | — | 2.5 V or 3.3 V (MultiVolt) |
| Programming Technology | — | EEPROM (non-volatile) |
| In-System Programming | — | IEEE Std. 1532 / JTAG (IEEE Std. 1149.1) |
| Ball Pitch | — | 1.0 mm |