EPM3512AFC256-7 vs EPM3512AQC20-10 Vergleich
Detaillierter Direktvergleich von EPM3512AFC256-7 von Intel und EPM3512AQC20-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPM3512AFC256-7 - 512-Macrocell MAX 3000A CPLD, 7.5ns, BGA-256 | Intel
EPM3512AFC256-7 ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EPM3512AFC256-7 | EPM3512AQC20-10 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $58,40 | $21,10 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| User I/O Pins | 212 | 100 |
| Usable Gates | 10,000 | — |
| Pin-to-Pin Logic Delay | 7.5 ns | — |
| Counter Frequency (max) | 227.3 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.0 V to 3.6 V (3.3 V typ.) | — |
| I/O Voltage (VCCIO) | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Gehäuse | 256-ball FineLine BGA (FBGA-256) | PQFP-240 (QC20 designation per Altera ordering code) |
| Programming | EEPROM, IEEE 1149.1 JTAG ISP (IEEE 1532-compliant) | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature grade] | 0C to +70C (commercial) |
| Montageart | Surface Mount | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Compliant (lead-free PQFP package) |
| Configuration Memory | Non-volatile EEPROM | — |
| Macrocells per LAB | — | 32 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Frequency (fCNT) | — | 116.3 MHz |
| Supply Voltage VCCINT | — | 5.0 V |
| MultiVolt I/O Voltages | — | 5.0 V / 3.3 V / 2.5 V / 1.8 V |
| Programming Interface | — | IEEE 1149.1 (JTAG) - In-System Programmable |
| Process Technology | — | 0.30 µm EEPROM CMOS |