EPM3512AFI256-7 vs EPM3512AFC256-10 Vergleich
Detaillierter Direktvergleich von EPM3512AFI256-7 von Altera und EPM3512AFC256-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3512AFI256-7 | EPM3512AFC256-10 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $15,95 | $17,50 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 10,000 |
| Logic Array Blocks (LABs) | 32 (16 macrocells each) | 16 |
| User I/O Pins | 208 | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | 10 ns |
| Maximum Operating Frequency | [DATA_NEEDED: fMAX value] | — |
| Supply Voltage VCCINT | 3.3 V | — |
| MultiVolt I/O Voltage | 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant | — |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| Gehäuse | 256-ball FBGA (Fine-Pitch BGA), 17 mm × 17 mm, 1.0 mm pitch | 256-pin FBGA |
| In-System Programmability | IEEE Std. 1532 compliant via JTAG | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) |
| Boundary-Scan Test | IEEE Std. 1149.1 (JTAG) | — |
| Operating Temperature (Industrial) | -40 °C to +85 °C | — |
| RoHS-Status | [DATA_NEEDED: confirm from data] | unknown |
| Montageart | Surface Mount (BGA) | Surface Mount |
| Maximum I/O Pins | — | 208 |
| Maximum Counter Frequency | — | 87 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5-V tolerant |
| Programmable Technology | — | CMOS EEPROM |
| Betriebstemperaturbereich | — | [DATA_NEEDED: industrial/commercial operating temperature range] |
| Pin-Anzahl | — | 256 |
| Architecture | — | MAX (Multiple Array matriX) EEPROM-based |