EPM3512AQ208-10N vs EPM3512AQC20-10 Vergleich
Detaillierter Direktvergleich von EPM3512AQ208-10N von Altera und EPM3512AQC20-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3512AQ208-10N | EPM3512AQC20-10 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $21,40 | $21,10 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | — |
| User I/Os | 172 | — |
| Logic Array Blocks (LABs) | 32 | 16 |
| Gehäuse | 208-pin PQFP | PQFP-240 (QC20 designation per Altera ordering code) |
| Speed Grade | -10 (10 ns pin-to-pin delay) | — |
| Pin-to-Pin Delay (tPD) | 4.5 ns (typical) | 10 ns |
| Maximum Frequency (fCNT) | 227.3 MHz | 116.3 MHz |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V, 3.3 V, or 5.0 V | — |
| Process Technology | CMOS EEPROM | 0.30 µm EEPROM CMOS |
| Programming Interface | IEEE Std. 1532 (JTAG) ISP | IEEE 1149.1 (JTAG) - In-System Programmable |
| Operating Temperature (Industrial) | -40 C to +85 C | — |
| Montageart | Surface Mount | — |
| RoHS-Status | unknown | Compliant (lead-free PQFP package) |
| Macrocells per LAB | — | 32 |
| User I/O Pins | — | 100 |
| Supply Voltage VCCINT | — | 5.0 V |
| MultiVolt I/O Voltages | — | 5.0 V / 3.3 V / 2.5 V / 1.8 V |
| Betriebstemperatur | — | 0C to +70C (commercial) |