EPM3512AQ208-10N vs EPM3512AQC208-10N Vergleich
Detaillierter Direktvergleich von EPM3512AQ208-10N von Altera und EPM3512AQC208-10N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3512AQ208-10N | EPM3512AQC208-10N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $21,40 | $42,80 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | Up to 10,000 |
| User I/Os | 172 | 172 |
| Logic Array Blocks (LABs) | 32 | 16 |
| Gehäuse | 208-pin PQFP | 208-pin PQFP (Plastic Quad Flat Pack) |
| Speed Grade | -10 (10 ns pin-to-pin delay) | -10 |
| Pin-to-Pin Delay (tPD) | 4.5 ns (typical) | — |
| Maximum Frequency (fCNT) | 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V, 3.3 V, or 5.0 V | — |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Programming Interface | IEEE Std. 1532 (JTAG) ISP | — |
| Operating Temperature (Industrial) | -40 C to +85 C | — |
| Montageart | Surface Mount | — |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS status not in verified web data] |
| Versorgungsspannung | — | 3.3 V |
| Pin-to-Pin Delay | — | 4.5 ns (-10 speed grade) |
| Maximum Internal Frequency | — | 227.3 MHz |
| In-System Programming | — | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Built-in, IEEE 1149.1 compliant |
| I/O Standards | — | MultiVolt (1.8V / 2.5V / 3.3V) |
| Betriebstemperatur | — | 0 C to 70 C (commercial) |