EPM3512AQC20-10 vs EPM3512AQC208-10S Vergleich

Detaillierter Direktvergleich von EPM3512AQC20-10 von Altera und EPM3512AQC208-10S von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM3512AQC20-10 EPM3512AQC208-10S
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $21,10 $9,75
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 512
Logic Array Blocks (LABs) 16 32 (16 macrocells each)
Macrocells per LAB 32 —
User I/O Pins 100 —
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Frequency (fCNT) 116.3 MHz —
Supply Voltage VCCINT 5.0 V —
MultiVolt I/O Voltages 5.0 V / 3.3 V / 2.5 V / 1.8 V —
Programming Interface IEEE 1149.1 (JTAG) - In-System Programmable —
Process Technology 0.30 µm EEPROM CMOS EEPROM-based CMOS
Gehäuse PQFP-240 (QC20 designation per Altera ordering code) 208-pin FineLine BGA-256
Betriebstemperatur 0C to +70C (commercial) 0C to +70C (commercial)
RoHS-Status Compliant (lead-free PQFP package) [DATA_NEEDED: rohs_status]
Usable Gates — 1750
User I/Os — 208
Speed Grade — -10 (tPD1 = 7.5 ns)
Propagation Delay (tPD1) — 7.5 ns (pin-to-pin)
Supply Voltage - VCCINT (internal) — 3.3 V
Supply Voltage - VCCIO (I/O) — 2.5 V, 3.3 V, or 5.0 V (MultiVolt)
Programming Technology — CMOS EEPROM
In-System Programmability (ISP) — Yes (IEEE Std. 1149.1 JTAG)
PCI Compliance — Yes (PCI Local Bus Specification Rev 2.2)
Boundary-Scan (JTAG) — Yes (1149.1 compliant)
Program/Erase Endurance — 100 cycles minimum
Logic Family — CMOS

Datenblätter & Ressourcen

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