EPM3512AQC208-10 vs EPM3512AQ208-10N Vergleich
Detaillierter Direktvergleich von EPM3512AQC208-10 von Altera und EPM3512AQ208-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3512AQC208-10 | EPM3512AQ208-10N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $22,10 | $21,40 |
| Family | MAX 3000A | MAX 3000A |
| Usable Gates | 10,000 | 10,000 |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 32 | 32 |
| User I/Os | 208 | 172 |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Frequency (fCNT) | 116.3 MHz | 227.3 MHz |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (IEEE Std. 1532) | — |
| JTAG Boundary Scan | Yes (IEEE 1149.1) | — |
| PCI Compliance | PCI Local Bus Spec Rev. 2.2 (-10 speed grade) | — |
| Gehäuse | 208-pin PQFP | 208-pin PQFP |
| Betriebstemperatur | 0C to +70 C (commercial) | — |
| RoHS-Status | [DATA_NEEDED: RoHS status not in verified data] | unknown |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Speed Grade | — | -10 (10 ns pin-to-pin delay) |
| Pin-to-Pin Delay (tPD) | — | 4.5 ns (typical) |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V, 3.3 V, or 5.0 V |
| Process Technology | — | CMOS EEPROM |
| Programming Interface | — | IEEE Std. 1532 (JTAG) ISP |
| Operating Temperature (Industrial) | — | -40 C to +85 C |
| Montageart | — | Surface Mount |