EPM3512AQC208-10S vs EPM3512AQC208-10 Vergleich
Detaillierter Direktvergleich von EPM3512AQC208-10S von Altera und EPM3512AQC208-10 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3512AQC208-10S | EPM3512AQC208-10 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $22,10 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 1750 | 10,000 |
| Logic Array Blocks (LABs) | 32 (16 macrocells each) | 32 |
| Gehäuse | 208-pin FineLine BGA-256 | 208-pin PQFP |
| User I/Os | 208 | 208 |
| Speed Grade | -10 (tPD1 = 7.5 ns) | — |
| Propagation Delay (tPD1) | 7.5 ns (pin-to-pin) | — |
| Supply Voltage - VCCINT (internal) | 3.3 V | — |
| Supply Voltage - VCCIO (I/O) | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) | — |
| Programming Technology | CMOS EEPROM | — |
| In-System Programmability (ISP) | Yes (IEEE Std. 1149.1 JTAG) | — |
| PCI Compliance | Yes (PCI Local Bus Specification Rev 2.2) | PCI Local Bus Spec Rev. 2.2 (-10 speed grade) |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70 C (commercial) |
| Boundary-Scan (JTAG) | Yes (1149.1 compliant) | — |
| Program/Erase Endurance | 100 cycles minimum | — |
| Logic Family | CMOS | — |
| Process Technology | EEPROM-based CMOS | — |
| RoHS-Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status not in verified data] |
| Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Frequency (fCNT) | — | 116.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (IEEE Std. 1532) |
| JTAG Boundary Scan | — | Yes (IEEE 1149.1) |