EPM3512AQC208-10S vs EPM3512AQC208-10N Vergleich

Detaillierter Direktvergleich von EPM3512AQC208-10S von Altera und EPM3512AQC208-10N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM3512AQC208-10S EPM3512AQC208-10N
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,75 $42,80
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 512
Usable Gates 1750 Up to 10,000
Logic Array Blocks (LABs) 32 (16 macrocells each) 16
Gehäuse 208-pin FineLine BGA-256 208-pin PQFP (Plastic Quad Flat Pack)
User I/Os 208 172
Speed Grade -10 (tPD1 = 7.5 ns) -10
Propagation Delay (tPD1) 7.5 ns (pin-to-pin) —
Supply Voltage - VCCINT (internal) 3.3 V —
Supply Voltage - VCCIO (I/O) 2.5 V, 3.3 V, or 5.0 V (MultiVolt) —
Programming Technology CMOS EEPROM —
In-System Programmability (ISP) Yes (IEEE Std. 1149.1 JTAG) —
PCI Compliance Yes (PCI Local Bus Specification Rev 2.2) —
Betriebstemperatur 0C to +70C (commercial) 0 C to 70 C (commercial)
Boundary-Scan (JTAG) Yes (1149.1 compliant) —
Program/Erase Endurance 100 cycles minimum —
Logic Family CMOS —
Process Technology EEPROM-based CMOS CMOS EEPROM
RoHS-Status [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS status not in verified web data]
Versorgungsspannung — 3.3 V
Pin-to-Pin Delay — 4.5 ns (-10 speed grade)
Maximum Internal Frequency — 227.3 MHz
In-System Programming — IEEE Std. 1149.1 JTAG, IEEE Std. 1532
Boundary-Scan Test (BST) — Built-in, IEEE 1149.1 compliant
I/O Standards — MultiVolt (1.8V / 2.5V / 3.3V)

Datenblätter & Ressourcen

Alle Produkte durchsuchen BOM erstellen Angebot anfordern