EPM3512AQC208-10S vs EPM3512AQC208-2 Vergleich

Detaillierter Direktvergleich von EPM3512AQC208-10S von Altera und EPM3512AQC208-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM3512AQC208-10S EPM3512AQC208-2
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,75 $18,75
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 512
Usable Gates 1750 —
Logic Array Blocks (LABs) 32 (16 macrocells each) 16
Gehäuse 208-pin FineLine BGA-256 PQFP-208 (QC)
User I/Os 208 —
Speed Grade -10 (tPD1 = 7.5 ns) -2
Propagation Delay (tPD1) 7.5 ns (pin-to-pin) —
Supply Voltage - VCCINT (internal) 3.3 V —
Supply Voltage - VCCIO (I/O) 2.5 V, 3.3 V, or 5.0 V (MultiVolt) —
Programming Technology CMOS EEPROM —
In-System Programmability (ISP) Yes (IEEE Std. 1149.1 JTAG) —
PCI Compliance Yes (PCI Local Bus Specification Rev 2.2) —
Betriebstemperatur 0C to +70C (commercial) —
Boundary-Scan (JTAG) Yes (1149.1 compliant) —
Program/Erase Endurance 100 cycles minimum 100 cycles (typical)
Logic Family CMOS —
Process Technology EEPROM-based CMOS 0.30 µm EEPROM
RoHS-Status [DATA_NEEDED: rohs_status] Non-compliant (legacy PQFP)
User I/O Pins — 172
Supply Voltage (Core) — 3.3 V
Output Drive Voltage — 2.5 V / 3.3 V programmable
Input Voltage Tolerance — 2.5 V / 3.3 V / 5.0 V
In-System Programmability — Yes (IEEE 1149.1 JTAG)
User I/O Banks — 4
Betriebstemperaturbereich — Commercial (0C to +70C)
Montageart — Surface Mount
Lead-Free — No (SnPb lead finish)
Security Bit — Yes (programmable)

Datenblätter & Ressourcen

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