EPM3512AQC208-7 vs EPM3512AQC208-2 Vergleich
Detaillierter Direktvergleich von EPM3512AQC208-7 von Intel und EPM3512AQC208-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPM3512AQC208-7 - MAX 3000A CPLD, 512 Macrocells, 7.5ns, 208-PQFP | Intel
EPM3512AQC208-7 NrndSpezifikationsvergleich
| Parameter | EPM3512AQC208-7 | EPM3512AQC208-2 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $41,72 | $18,75 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Counter Frequency (fCNT) | 116.3 MHz | — |
| User I/Os | 172 | — |
| Logic Elements / LEs | N/A (CPLD macrocell architecture) | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Standards Supported | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) | — |
| Gehäuse | 208-Pin PQFP (FQFP, gull-wing) | PQFP-208 (QC) |
| Betriebstemperatur | 0 C to +70 C (commercial) | — |
| Programming | In-System Programmable via JTAG (IEEE Std. 1532) | — |
| Process Technology | CMOS EEPROM, 0.30 um | 0.30 µm EEPROM |
| RoHS-Status | Compliant | Non-compliant (legacy PQFP) |
| Lead-Free | Yes | No (SnPb lead finish) |
| User I/O Pins | — | 172 |
| Logic Array Blocks (LABs) | — | 16 |
| Speed Grade | — | -2 |
| Supply Voltage (Core) | — | 3.3 V |
| Output Drive Voltage | — | 2.5 V / 3.3 V programmable |
| Input Voltage Tolerance | — | 2.5 V / 3.3 V / 5.0 V |
| Program/Erase Endurance | — | 100 cycles (typical) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| User I/O Banks | — | 4 |
| Betriebstemperaturbereich | — | Commercial (0C to +70C) |
| Montageart | — | Surface Mount |
| Security Bit | — | Yes (programmable) |