EPM3512AQC208-7N vs EPM3512AQC210-7 Vergleich
Detaillierter Direktvergleich von EPM3512AQC208-7N von Altera und EPM3512AQC210-7 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera
EPM3512AQC208-7N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM3512AQC208-7N | EPM3512AQC210-7 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $41,41 | $21,85 |
| Family | MAX 3000A | MAX 3000A |
| Logic Capacity | 512 macrocells, 10,000 usable gates | — |
| Logic Array Blocks (LABs) | 32 | 16 |
| Macrocells per LAB | 16 | — |
| User I/Os | 172 | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Frequency (fCNT) | 116.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | — |
| I/O Bank Count | 4 (MultiVolt) | — |
| Supported I/O Standards | 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS | — |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| Configuration | Non-volatile EEPROM, in-system programmable (ISP) | — |
| JTAG Interface | IEEE 1149.1 BST + IEEE 1532 ISP | — |
| Gehäuse | 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing) | PQFP-208 |
| Betriebstemperatur | 0 °C to +70 °C (commercial) | [DATA_NEEDED: operating temperature range] |
| RoHS-Status | Compliant | [DATA_NEEDED: RoHS compliance] |
| Speed Grade | -7 | 7 ns |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 512 |
| Maximum User I/O Pins | — | 172 |
| Dedicated Input Pins | — | 12 |
| Pin-Anzahl | — | 208 |
| Montageart | — | Surface Mount |
| Operating Voltage (Core) | — | 3.3 V |
| Min Supply Voltage | — | 3.0 V |
| Max Supply Voltage | — | 3.6 V |
| I/O Voltage Support | — | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) |
| Pin-to-Pin Delay | — | 7 ns (speed grade -7) |
| In-System Programmability | — | Yes (JTAG, IEEE 1149.1) |
| Non-Volatile Configuration | — | Yes (EEPROM-based) |