EPM3512AQC20810N vs EPM3512AQC208-10N Vergleich
Detaillierter Direktvergleich von EPM3512AQC20810N von Altera und EPM3512AQC208-10N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3512AQC20810N | EPM3512AQC208-10N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $39,75 | $42,80 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 512 | — |
| Usable Gates | 10,000 | Up to 10,000 |
| User I/Os | 172 | 172 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Propagation Delay (tPD) | 10 ns | — |
| Core Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage (VCCIO) | 3.3 V (5.0 V tolerant I/O) | — |
| Gehäuse | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin PQFP (Plastic Quad Flat Pack) |
| Configuration Memory | EEPROM (non-volatile, instant-on) | — |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE 1532 ISP) | — |
| Maximum Frequency | [DATA_NEEDED: fMAX] | — |
| Betriebstemperatur | [DATA_NEEDED: industrial/commercial grade range] | 0 C to 70 C (commercial) |
| RoHS-Status | [DATA_NEEDED: lead-free/RoHS status] | [DATA_NEEDED: RoHS status not in verified web data] |
| Montageart | Surface Mount | — |
| MSL-Level | [DATA_NEEDED: MSL rating] | — |
| Macrocells | — | 512 |
| Versorgungsspannung | — | 3.3 V |
| Pin-to-Pin Delay | — | 4.5 ns (-10 speed grade) |
| Maximum Internal Frequency | — | 227.3 MHz |
| Speed Grade | — | -10 |
| Process Technology | — | CMOS EEPROM |
| In-System Programming | — | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Built-in, IEEE 1149.1 compliant |
| I/O Standards | — | MultiVolt (1.8V / 2.5V / 3.3V) |