EPM3512AQI208-7 vs EPM3512AQI208-7N Vergleich
Detaillierter Direktvergleich von EPM3512AQI208-7 von Altera und EPM3512AQI208-7N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3512AQI208-7 | EPM3512AQI208-7N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,85 | $18,45 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 10,000 | 10,000 |
| Macro Cells | 512 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum Operating Frequency | 116.3 MHz | 116.3 MHz |
| Speed Grade | -7 | 7 (7N suffix) |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: tPD in ns] | — |
| Core Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Programmability | Non-volatile, in-system programmable (IEEE Std. 1532) | — |
| JTAG Support | Yes (IEEE 1149.1 boundary scan + ISP) | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for PQFP-208] | [DATA_NEEDED: exact user I/O count for PQFP-208] |
| Gehäuse | 208-pin PQFP | 208-pin PQFP |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | -40C to +85C (industrial) | Industrial (per 'N' suffix) |
| Lead-Free / RoHS | Compliant per Altera product page | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 512 |
| Programming Interface | — | IEEE 1149.1 JTAG (in-system programmable) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Pin-Anzahl | — | 208 |
| RoHS-Status | — | Compliant |
| Propagation Delay (tPD) | — | [DATA_NEEDED: tPD in ns per speed grade 7] |