EPM3512ATC144 vs EPM3256ATC144-7N Vergleich
Detaillierter Direktvergleich von EPM3512ATC144 von Altera und EPM3256ATC144-7N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3256ATC144-7N - MAX 3000A CPLD 256 Macro 7.5ns | Altera
EPM3256ATC144-7N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPM3512ATC144 | EPM3256ATC144-7N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,75 | $17,20 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 212 | — |
| Gehäuse | TQFP-144 (20x20 mm) | 144-pin TQFP |
| Core Supply Voltage | 3.3 V | — |
| Programming Technology | EEPROM (in-system programmable) | — |
| JTAG Interface | IEEE Std. 1149.1 (4-pin) | — |
| Maximum Frequency | 116 MHz | — |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns] | 7.5 ns |
| Product Terms per Macrocell | 32 (expandable) | — |
| I/O Standards | LVTTL, LVCMOS, 2.5 V/3.3 V/5 V tolerant | — |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| Montageart | Surface Mount | Surface Mount |
| MSL-Level | 3 | — |
| RoHS-Status | Compliant (lead-free suffix variants available) | Compliant |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Macro Cells | — | 256 |
| Logic Gates (usable) | — | 5,000 |
| Number of Logic Array Blocks (LABs) | — | 16 |
| User I/Os | — | 116 |
| Maximum Internal Frequency | — | 126.6 MHz |
| Supply Voltage (VCCIO) | — | 3.0 V to 3.6 V |
| Programmable Logic Technology | — | CMOS EEPROM-based |
| In-System Programmable (ISP) | — | Yes (3.3 V) |
| Logic Family | — | CMOS |
| JTAG Support | — | IEEE 1149.1 boundary-scan |