EPM5016PC-1 vs EPM5016LC-17 Vergleich
Detaillierter Direktvergleich von EPM5016PC-1 von Altera und EPM5016LC-17 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5016PC-1 | EPM5016LC-17 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $10,95 |
| Family | MAX 5000 EPLD | MAX 5000 EPLD |
| Macrocells | 16 | 16 |
| Usable Gates | 200 | — |
| Logic Array Blocks (LABs) | 1 | — |
| Propagation Delay (tPD) | 35 ns | 17 ns |
| Maximum Frequency (fMAX) | 62 MHz | — |
| Setup Time (tSU) | [DATA_NEEDED: setup time ns] | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Supply Current (ICC) | 50 mA typical | — |
| Betriebstemperatur | 0 C to +70 C (commercial) | [DATA_NEEDED: temperature grade] |
| Gehäuse | PDIP-20 (plastic DIP, through-hole) | Windowed Ceramic DIP (LC) |
| Pin-Anzahl | 20 | — |
| Configuration Memory | CMOS EEPROM (UV-erasable) | — |
| Programming Interface | Altera 4-pin JTAG-style (MasterBlaster / ByteBlaster) | — |
| RoHS-Status | Non-compliant (PDIP with SnPb leads, pre-RoHS era) | [DATA_NEEDED: RoHS compliance] |
| Technology | — | CMOS, UV-erasable |
| Product Terms | — | 160 |
| Dedicated Inputs | — | 7 |
| I/O Pins | — | 8 |
| Total Input Pins | — | 16 |
| Outputs | — | 8 |
| External Clock Inputs | — | 1 |
| Architecture | — | PAL-type with Programmable Interconnect Array (PIA) |
| Versorgungsspannung | — | [DATA_NEEDED: VCC range] |
| Logic Compatibility | — | TTL/CMOS |