EPM5032DC-2 vs EPM5016DC-15 Vergleich

Detaillierter Direktvergleich von EPM5032DC-2 von Altera und EPM5016DC-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5032DC-2 EPM5016DC-15
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $8,75 $10,75
Product Type CPLD (Complex Programmable Logic Device) EPLD (Erasable Programmable Logic Device)
Series MAX 5000 —
Macrocells 32 16
Usable Gates (typical) 600 —
Logic Array Blocks (LABs) 4 2
Gehäuse 20-pin CDIP (Ceramic DIP) Ceramic DIP-24 (windowed)
Speed Grade -2 (tPD ~25 ns, commercial) —
Configuration Memory EPROM (one-time programmable per generation; UV-erasable variants exist) Non-volatile UV-erasable EPROM
Supply Voltage (VCC) 5 V (single supply, +/-5%) 4.75 V to 5.25 V
Betriebstemperatur 0C to +70C (commercial grade) 0 °C to 70 °C (commercial)
Programmable Pins / I/O 20 pins (JEDEC-standard 0.300" ceramic DIP) —
Programming Interface Altera ByteBlaster / parallel-port JTAG-style ISP —
Interconnect Programmable Interconnect Array (PIA) with deterministic timing —
RoHS-Status [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS] [DATA_NEEDED: RoHS status - pre-RoHS era part, likely non-compliant]
Montageart Through-Hole (DIP) Through-Hole
MSL-Level Not applicable (through-hole hermetic ceramic) —
Device Family — MAX 5000
Dedicated Inputs — 4
User I/O Pins — 12
Pin-to-Pin Delay (tpd) — 15 ns
Maximum Frequency (fmax) — 71 MHz
Programming Voltage (VPP) — 12.75 V
Process Technology — CMOS EPROM
Lead Finish — [DATA_NEEDED: lead-free status]

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