EPM5032DC20 vs EPM5016DC-20 Vergleich
Detaillierter Direktvergleich von EPM5032DC20 von Altera und EPM5016DC-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5032DC20 | EPM5016DC-20 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,20 | $16,50 |
| Device Family | MAX 5000 | — |
| Product Type | UV-erasable PLD (CPLD class) | — |
| Macrocells | 32 | 16 |
| Usable Gates | 600 | — |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| Maximum Frequency (Fmax) | 71.4 MHz | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 16 (bidirectional) | 8 |
| Total Inputs (max) | 24 | — |
| Output Macrocells | 16 | — |
| Clock Inputs | 1 (global) | — |
| Architecture | PAL-type with Programmable Interconnect Array (PIA) | PAL-type macrocell with Programmable Interconnect Array (PIA) |
| Process Technology | CMOS | CMOS, UV-erasable |
| Gehäuse | 20-pin Ceramic DIP (DC) with UV window | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Montageart | Through-Hole (DIP) | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Family | — | MAX 5000 |
| Device Type | — | EPLD (UV-Erasable Programmable Logic Device) |
| Product Terms | — | 160 |
| Maximale Taktfrequenz | — | 62.5 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Nominal Supply Voltage | — | 5.0 V |
| Package Type | — | 20-pin Ceramic DIP (Cerdip) with UV window |
| Package Suffix Code | — | DC = Ceramic DIP, Commercial |
| Speed Grade | — | -20 = 20 ns tPD |
| Programming Method | — | UV erase + EPROM-style programming via Altera programming hardware |