EPM5032DC20 vs EPM5032DC-2 Vergleich

Detaillierter Direktvergleich von EPM5032DC20 von Altera und EPM5032DC-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5032DC20 EPM5032DC-2
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $8,20 $8,75
Device Family MAX 5000 —
Product Type UV-erasable PLD (CPLD class) CPLD (Complex Programmable Logic Device)
Macrocells 32 32
Usable Gates 600 —
Propagation Delay (tPD) 20 ns —
Maximum Frequency (Fmax) 71.4 MHz —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) 5 V (single supply, +/-5%)
Dedicated Inputs 7 —
I/O Pins 16 (bidirectional) —
Total Inputs (max) 24 —
Output Macrocells 16 —
Clock Inputs 1 (global) —
Architecture PAL-type with Programmable Interconnect Array (PIA) —
Process Technology CMOS —
Gehäuse 20-pin Ceramic DIP (DC) with UV window 20-pin CDIP (Ceramic DIP)
Betriebstemperatur [DATA_NEEDED: operating temperature range] 0C to +70C (commercial grade)
Montageart Through-Hole (DIP) Through-Hole (DIP)
RoHS-Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS]
Series — MAX 5000
Usable Gates (typical) — 600
Logic Array Blocks (LABs) — 4
Speed Grade — -2 (tPD ~25 ns, commercial)
Configuration Memory — EPROM (one-time programmable per generation; UV-erasable variants exist)
Programmable Pins / I/O — 20 pins (JEDEC-standard 0.300" ceramic DIP)
Programming Interface — Altera ByteBlaster / parallel-port JTAG-style ISP
Interconnect — Programmable Interconnect Array (PIA) with deterministic timing
MSL-Level — Not applicable (through-hole hermetic ceramic)

Datenblätter & Ressourcen

Alle Produkte durchsuchen BOM erstellen Angebot anfordern