EPM5032DI-20 vs EPM5032DC20 Vergleich
Detaillierter Direktvergleich von EPM5032DI-20 von Intel und EPM5032DC20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5032DI-20 | EPM5032DC20 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,75 | $8,20 |
| Family | MAX 5000 (Altera legacy EPLD) | — |
| Architecture | CMOS PAL-type EPLD with PIA | PAL-type with Programmable Interconnect Array (PIA) |
| Macrocells | 32 | 32 |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | — |
| Product Terms | 320 (maximum) | — |
| Flip-Flops | 16 (one per macrocell) | — |
| Maximale Taktfrequenz | 62.5 MHz | — |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | — |
| Gehäuse | Ceramic DIP-20 (windowed, UV-erasable) | 20-pin Ceramic DIP (DC) with UV window |
| Betriebstemperatur | Industrial (per 'I' suffix) | [DATA_NEEDED: operating temperature range] |
| Programming | UV-erasable CMOS, JEDEC fuse file | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable PLD (CPLD class) |
| Usable Gates | — | 600 |
| Propagation Delay (tPD) | — | 20 ns |
| Maximum Frequency (Fmax) | — | 71.4 MHz |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| I/O Pins | — | 16 (bidirectional) |
| Total Inputs (max) | — | 24 |
| Output Macrocells | — | 16 |
| Clock Inputs | — | 1 (global) |
| Process Technology | — | CMOS |
| Montageart | — | Through-Hole (DIP) |