EPM5032DI-25 vs EPM5032DC-25 Vergleich
Detaillierter Direktvergleich von EPM5032DI-25 von Altera und EPM5032DC-25 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5032DI-25 | EPM5032DC-25 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $18,20 | $3,55 |
| Family | MAX 5000 | — |
| Device Type | UV-erasable Programmable Logic Device (PLD) | UV Erasable Programmable Logic Device (EPLD) |
| Architecture | PAL-type, CMOS, AND-OR sum-of-products | PAL-Type, Single-LAB, 32-Macrocell |
| Macrocells | 32 | 32 |
| Product Terms | 320 | — |
| Logic Gates | [DATA_NEEDED: equivalent gate count] | — |
| Dedicated Inputs | 7 | — |
| Bidirectional I/O Pins | 16 | — |
| Total Array Inputs | 24 | — |
| Registered Outputs | 16 | — |
| Global Clocks | 1 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | — |
| Versorgungsspannung | 5 V | — |
| Process Technology | CMOS | CMOS, EPROM (UV-Erasable) |
| Gehäuse | Ceramic DIP, windowed (UV-erasable) | CDIP-28 (Windowed Ceramic DIP-28) |
| Pin-Anzahl | [DATA_NEEDED: exact pin count - 24 or 28] | — |
| Betriebstemperatur | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| I/O Standard | TTL-compatible | — |
| Programmability | UV-erasable, EPROM-based | — |
| Development Tool | MAX+PLUS II / A+PLUS | — |
| RoHS-Status | [DATA_NEEDED: likely non-compliant due to ceramic DIP] | Lead Free / RoHS Compliant (per distributor listings) |
| Lifecycle | Not Recommended for New Designs (NRND) | — |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |
| Product Family | — | MAX 5000 |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Maximum Counter Frequency (fCNT) | — | [DATA_NEEDED: maximum counter frequency] |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time] |
| Number of Dedicated Inputs | — | 32 (in DIP-28 pinout) |
| Number of I/O Pins | — | 22 (in DIP-28 pinout, 4 used as dedicated inputs) |
| Output Structure | — | Programmable I/O with output enable |
| Flip-Flop Configuration | — | D, T, JK, or SR (programmable) |
| Programming Method | — | UV erase + Altera/Intel MAX+PLUS II programmer |
| Erasure Method | — | UV light through ceramic window |