EPM5032PC-20 vs EPM5032DC-25 Vergleich
Detaillierter Direktvergleich von EPM5032PC-20 von Altera und EPM5032DC-25 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5032PC-20 | EPM5032DC-25 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,05 | $3,55 |
| Device Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | UV Erasable Programmable Logic Device (EPLD) |
| Programming Type | OTP (One-Time Programmable) | — |
| Macrocells | 32 | 32 |
| Usable Gates | 600 | — |
| Logic Blocks | 2 Logic Array Blocks | — |
| Product Terms | 320 | — |
| Dedicated Inputs | 24 | — |
| Bidirectional I/O Lines | 16 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Maximale Taktfrequenz | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) | — |
| Technology | CMOS, 0.65 um process | — |
| Architecture | PAL-type macrocells with Programmable Interconnect Array (PIA) | PAL-Type, Single-LAB, 32-Macrocell |
| Gehäuse | PDIP-28 (Plastic DIP, 28-pin) | CDIP-28 (Windowed Ceramic DIP-28) |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Montageart | Through-Hole | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Lead Free / RoHS Compliant (per distributor listings) |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |
| Product Family | — | MAX 5000 |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Maximum Counter Frequency (fCNT) | — | [DATA_NEEDED: maximum counter frequency] |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time] |
| Number of Dedicated Inputs | — | 32 (in DIP-28 pinout) |
| Number of I/O Pins | — | 22 (in DIP-28 pinout, 4 used as dedicated inputs) |
| Process Technology | — | CMOS, EPROM (UV-Erasable) |
| Output Structure | — | Programmable I/O with output enable |
| Flip-Flop Configuration | — | D, T, JK, or SR (programmable) |
| Programming Method | — | UV erase + Altera/Intel MAX+PLUS II programmer |
| Erasure Method | — | UV light through ceramic window |