EPM5064JC-1 vs EPM5064LC Vergleich

Detaillierter Direktvergleich von EPM5064JC-1 von Altera und EPM5064LC von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5064JC-1 EPM5064LC
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus NRND Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $18,25 $7,10
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 64 64
Usable Gates 1250 (typical) 1.25K
Logic Elements 128 (Logic Array Blocks) —
Maximum Operating Frequency 33.3 MHz (fCNT) —
Pin-to-Pin Delay (tPD) [DATA_NEEDED: tPD typical/max in ns] —
Supply Voltage (VCC) 5 V nominal (4.75 V – 5.25 V) 4.75 V to 5.25 V
Process Technology 0.8 µm CMOS CMOS EPROM
Programmable Pins 36 (typical I/O, 44-pin PLCC) —
Dedicated Inputs [DATA_NEEDED: dedicated input count] —
Gehäuse 44-pin PLCC (J-lead, windowed ceramic) PLCC-44 (LCC-44, J-lead)
Montageart Surface Mount (PLCC socket recommended) Surface Mount
Betriebstemperatur 0 °C to +70 °C (commercial, -JC suffix) 0C to +70C (Commercial)
Erasure Method UV-erasable through quartz window —
Programming Method Altera Logic Programmer + MasterBlaster/ByteBlasterMV —
JTAG Boundary Scan Not supported (classic MAX architecture) —
RoHS-Status Non-compliant (windowed ceramic, contains Pb in glass frit) [DATA_NEEDED: RoHS status - pre-RoHS legacy part, likely non_compliant]
Military/Avionics SMD 5962-01-417-3750 (QML variant: EPM5064JM/883) —
Programming Type — OTP (One-Time-Programmable, UV-erasable EPROM)
Logic Array Blocks (LABs) — 4
Propagation Delay (tPD) — 55 ns
Total Inputs — 36 (7 dedicated + 29 I/O)
I/O Pins — 28 bidirectional + 4 dedicated input
Lead Free — [DATA_NEEDED: lead-free status]

Datenblätter & Ressourcen

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