EPM5064JC vs EPM5064JC-1 Vergleich
Detaillierter Direktvergleich von EPM5064JC von Altera und EPM5064JC-1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5064JC | EPM5064JC-1 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,10 | $18,25 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable PLD) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 64 | — |
| Usable Gates | 1,250 (approx.) | 1250 (typical) |
| Logic Array Inputs | 36 | — |
| Logic Array Outputs | 64 | — |
| Gehäuse | 68-pin PLCC (JEDEC) | 44-pin PLCC (J-lead, windowed ceramic) |
| Montageart | Surface Mount (socketed) | Surface Mount (PLCC socket recommended) |
| Supply Voltage (VCC) | 5 V (typical, 4.75 V - 5.25 V range) | 5 V nominal (4.75 V – 5.25 V) |
| I/O Logic Level | TTL / CMOS compatible | — |
| Configuration Memory | EPROM (UV-erasable window or OTP) | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature grade] | 0 °C to +70 °C (commercial, -JC suffix) |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: specific tPD grade value] | [DATA_NEEDED: tPD typical/max in ns] |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fCNT grade value] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | Non-compliant (windowed ceramic, contains Pb in glass frit) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL-Level | [DATA_NEEDED: MSL rating] | — |
| Programming Tool | Altera MAX+PLUS II / Quartus II (legacy device support) | — |
| Macro Cells | — | 64 |
| Logic Elements | — | 128 (Logic Array Blocks) |
| Maximum Operating Frequency | — | 33.3 MHz (fCNT) |
| Process Technology | — | 0.8 µm CMOS |
| Programmable Pins | — | 36 (typical I/O, 44-pin PLCC) |
| Dedicated Inputs | — | [DATA_NEEDED: dedicated input count] |
| Erasure Method | — | UV-erasable through quartz window |
| Programming Method | — | Altera Logic Programmer + MasterBlaster/ByteBlasterMV |
| JTAG Boundary Scan | — | Not supported (classic MAX architecture) |
| Military/Avionics SMD | — | 5962-01-417-3750 (QML variant: EPM5064JM/883) |