EPM5064JC vs EPM5064JC1 Vergleich

Detaillierter Direktvergleich von EPM5064JC von Altera und EPM5064JC1 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5064JC EPM5064JC1
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $7,10 $1,05
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable PLD) CPLD / EPLD (Erasable PLD)
Macrocells 64 64
Usable Gates 1,250 (approx.) 1.25K
Logic Array Inputs 36 —
Logic Array Outputs 64 —
Gehäuse 68-pin PLCC (JEDEC) 44-pin PLCC (J-Lead)
Montageart Surface Mount (socketed) —
Supply Voltage (VCC) 5 V (typical, 4.75 V - 5.25 V range) —
I/O Logic Level TTL / CMOS compatible —
Configuration Memory EPROM (UV-erasable window or OTP) —
Betriebstemperatur [DATA_NEEDED: operating temperature grade] —
Pin-to-Pin Delay (tPD) [DATA_NEEDED: specific tPD grade value] —
Maximum Frequency (fMAX) [DATA_NEEDED: fCNT grade value] —
RoHS-Status [DATA_NEEDED: RoHS compliance] unknown
Lead-Free [DATA_NEEDED: lead-free status] —
MSL-Level [DATA_NEEDED: MSL rating] —
Programming Tool Altera MAX+PLUS II / Quartus II (legacy device support) —
Logic Array Blocks (LABs) — 4
Maximum Operating Frequency (fCNT) — 62.5 MHz
External Clock Input (max) — 50 MHz
I/O Pins — 28
Dedicated Inputs — 7
Total Inputs — 36 (28 I/O + 7 dedicated + 1 clock)
Operating Voltage (VCC) — 5 V
Program Type — EPROM (one-time programmable, UV-erasable)
Process Technology — CMOS
Operating Temperature (JC suffix) — 0°C to +70°C (commercial)
Supply Current (ICC) — [DATA_NEEDED: ICC maximum]
Lead-Free Status — unknown

Datenblätter & Ressourcen

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