EPM5064LC-2 vs EPM5128GC-2 Vergleich

Detaillierter Direktvergleich von EPM5064LC-2 von Altera und EPM5128GC-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5064LC-2 EPM5128GC-2
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $8,40 $8,95
Device Family MAX 5000 —
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 64 128
Logic Array Blocks (LABs) 4 —
Logic Elements per LAB 16 —
Number of Inputs 36 (7 dedicated + 28 I/O) —
Number of I/O Pins 28 —
Number of Flip-Flops 28 —
Propagation Delay (tPD) 45 ns Approx. 25 ns (typical, -2 speed grade)
Maximum Internal Frequency 40 MHz —
Process Technology CMOS, OTP EPROM (UV-erasable base) —
Programmable Polarity Yes —
Programmable Output Enable Yes, per macrocell —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (nominal)
Betriebstemperatur -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source] 0C to +70C (commercial)
Gehäuse PLCC-44 (J-Lead, plastic) —
Montageart Surface Mount —
RoHS-Status [DATA_NEEDED: not specified in source] —
Programming Method Altera byte-wide / JTAG programmer —
Family — MAX 5000
Logic Elements / Gates — 2,500 usable gates
Number of Usable Gates — 2,500
Maximum Operating Frequency — 50 MHz
Package Type — 68-pin PGA (Pin Grid Array)
Package Code (per Partstack) — WPGA
Number of Terminals — 68
Programming Technology — UV-erasable EPROM
Grade (per Partstack) — COMMERCIAL
Terminal Form — PIN/PEG
Configuration Memory — Non-volatile, one-time programmable (erasable via UV)

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