EPM5064LI vs EPM5064JI-1 Vergleich
Detaillierter Direktvergleich von EPM5064LI von Altera und EPM5064JI-1 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5064LI | EPM5064JI-1 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $3,40 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | — |
| Number of Terminals | 44 | — |
| Package Code | QCCJ (PLCC-44, J-bend) | — |
| Package Shape | Square | — |
| Configuration Memory | UV-Erasable / OTP (EPROM-based) | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Operating Temperature Grade | Industrial | — |
| Maximale Taktfrequenz | 33.3 MHz | — |
| Propagation Delay (tPD) | 55 ns (typical) | [DATA_NEEDED: combinational tPD from datasheet] |
| I/O Pins | 28 bidirectional | — |
| Dedicated Inputs | 7 | — |
| Total User Inputs | 36 | — |
| Process Technology | 1-micron EPIC CMOS | CMOS, UV-erasable |
| Latch-up Immunity | 500 mA typical at 125 C | — |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: confirm RoHS status - legacy Altera part] | [DATA_NEEDED: not stated in provided data] |
| User I/O Pins | — | [DATA_NEEDED: user I/O count from datasheet] |
| Gehäuse | — | 68-pin PLCC (windowed ceramic) |
| Logic Elements | — | [DATA_NEEDED: total logic elements] |
| Versorgungsspannung | — | 5 V |
| Betriebstemperatur | — | [DATA_NEEDED: commercial vs industrial grade temp range] |
| Speed Grade | — | JI-1 (commercial, -10/-12/-15 family) |
| Programmability | — | UV-erasable (windowed package) |
| Data Retention | — | 25 years (per MAX 5000 datasheet) |