EPM5128JC-1 vs EPM5128GC-2 Vergleich
Detaillierter Direktvergleich von EPM5128JC-1 von Altera und EPM5128GC-2 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5128JC-1 | EPM5128GC-2 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $24,95 | $8,95 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | Erasable Programmable Logic Device (EPLD/CPLD) | — |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | — |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| Maximum Operating Frequency | 62.5 MHz | 50 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 40 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (nominal) |
| Technology | CMOS, UV-erasable EPROM | — |
| Gehäuse | 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier) | — |
| Montageart | Surface Mount | — |
| Betriebstemperatur | [DATA_NEEDED: temperature grade] | 0C to +70C (commercial) |
| Programming Interface | JTAG / Altera dedicated programmer | — |
| Configuration Memory | Non-volatile EPROM (UV-erasable) | Non-volatile, one-time programmable (erasable via UV) |
| RoHS-Status | non_compliant (ceramic windowed package) | — |
| Lebenszyklusstatus | Obsolete - last-time-buy inventory only | — |
| Logic Elements / Gates | — | 2,500 usable gates |
| Number of Usable Gates | — | 2,500 |
| Propagation Delay (tPD) | — | Approx. 25 ns (typical, -2 speed grade) |
| Package Type | — | 68-pin PGA (Pin Grid Array) |
| Package Code (per Partstack) | — | WPGA |
| Number of Terminals | — | 68 |
| Programming Technology | — | UV-erasable EPROM |
| Grade (per Partstack) | — | COMMERCIAL |
| Terminal Form | — | PIN/PEG |